1. Field of the Invention
This invention relates to a self-timed pipeline processor designed to access a memory by pipelining.
2. Description of the Related Art
A pipeline processor is one kind of computer architecture. The pipeline processor has a close resemblance in concept to the assembly line where workers do respective operations in each block. As for the pipeline processor, operations or the like are processed in parallel in each block, namely, in each pipeline stage thereby achieving high-speed data processing. A self-timed pipeline processor is one of the pipeline processors of this type.
FIG. 1 is a block diagram of a conventional self-timed pipeline processor, wherein numerals 1 through 4 represent data latch circuits, numerals 5 through 7 represent operating circuits for operating the data latched in the data latch circuits 1 through 4, and numerals 8 through 11 represent transfer control circuits for controlling the transfer of data between the data latch circuits. A numeral 12 designates a pipeline stage A consisting of the data latch circuit 1, transfer control circuit 8 and operating circuit 5, a numeral 13 designates a pipeline stage B consisting of the data latch circuit 2, transfer control circuit 9 and operating circuit 6, and a numeral 14 designates a pipeline stage C consisting of the data latch circuit 3, transfer control circuit 10 and operating circuit 7. T0 through T4 denote data transfer demanding signals for demanding the succeeding pipeline stage to permit the transfer of the data to a data latch circuit thereof. B1 through B4 denote data transfer permitting signals for indicating the data latch circuit in the succeeding pipeline stage is vacant, that is, able to accept the data from the preceding pipeline stage. D1 through D4 denote latch controlling signals having the same output logical values as the corresponding signals T1 through T4. When the latch controlling signal is active, the data inputted to each of the data latch circuits 1 through 4 is latched (the inputted data is determined). As for the transfer control circuits 8 through 11, a transfer control circuit disclosed in Japanese Patent Application Laid-Open No. 63-204355 (204355/1988) may be employed.
In the conventional pipeline processor of the aforementioned structure, assuming that the data is inputted from the preceding pipeline stage (not shown) to the pipeline stage A 12, when the permitting signal B1 is active, the demanding signal T1 turns active thereby turning the latch controlling signal D1 active with the same timing. Accordingly, the data is latched by the data latch circuit 1. Then, the demanding signal T1 is outputted to the transfer control circuit 9. T1 is the data transfer demanding signal for outputting the data latched in the data latch circuit 1 to the next pipeline stage B 13, and B2 is the data transfer permitting signal which turns active when the data is able to be latched by the data latch circuit 2 in the next pipeline stage B 13. When the permitting signal B2 turns active, the data is inputted from the pipeline stage A 12 to the data latch circuit 2 of the pipeline stage B 13. In other words, the data is transferred from the data latch circuit 1 to the data latch circuit 2. In the manner as described above, the data is transferred between the data latch circuits 1 and 2 while the transfer control circuits 8, 9 communicate with each other by the signals T1 and B1. The data read out from a memory (not shown) reaches the data latch circuit 1 of the pipeline stage A 12 thereby being latched, and against some bits of the latched data, for example, a logical operation is performed in the operation circuit 5. The data read out from the memory includes an instruction code for carrying out the operation and an operand necessary for the logical operation, which are taken out from the data latch circuit 1 to carry out the operation in the operation circuit 5. The operation result is outputted to the data latch circuit 2 of the next pipeline stage B 13 while the remaining bits without being used for the operation are outputted to the data latch circuit 2. Similarly, the operation is conducted in the operation circuit 6 of the pipeline stage B 13, the result of which is outputted to the data latch circuit 3 of the pipeline stage C 11. After the data read out from the memory is processed in each of the operation circuits 5, 6, 7 of the respective pipeline stages as described hereinabove, the result is written into a memory or outputted to the other peripheral circuit. That is, the data is transferred from the left to the right of the pipeline stages.
In the above-described structure of the conventional self-timed pipeline processor, when accessing the memory by using pipeline stages for the purpose of high-throughput, since the data are processed in parallel by pipeline stages, the reading of the data from the memory and the writing of the data therefrom may be disadvantageously overlapped.
Moreover, in the case where the continuous inputted data access the same address of the memory when the memory accesses are rushing, it may cause a malfunction of the pipeline processor. This is because in the conventional processor the memory reading is performed prior to the memory writing and therefore, the memory reading by the following data is processed before the memory writing by the preceding data is finished, and the proper data to be read out by the preceding data is not read out.